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EPM9320ALC84-10-Programmable Logic Device Family-ALTERA

EPM9320ALC84-10-Programmable Logic Device Family-ALTERA

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Application : The MAX 9000 family of in-system-programmable, high-density, high-performance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROM based MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed grade of the MAX 9000 family is compliant with the PCI Local Bus Specification, Revision 2.2. Table 3 shows the speed grades available for MAX 9000 devices.

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Minimum Order : 1 piece

Place of Origin : china

Category : Bus Parts

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Product Description
EPM9320ALC84-10-Programmable Logic Device Family-ALTERA

Product Feature
High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std 1149.1 Joint Test Action Group (JTAG) interface Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates 10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz

Product Specification/Models
The MAX 9000 family of in-system-programmable, high-density, high-performance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROM based MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed grade of the MAX 9000 family is compliant with the PCI Local Bus Specification, Revision 2.2. Table 3 shows the speed grades available for MAX 9000 devices.

Other Information
Picture/PDF is provided China Post / EMS / DHL / Fedex / UPS or others is optional


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